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YTD436
ISTC
ISDN BRI controller with S/T ref. pt. analog D/R
YTD436 is a high-performance communication LSI for the ISDN BRI user-network interface function (digital four-wire time-division full-duplex operation), supporting D channel layer 1 and layer 2 functions in one 100-pin SQFP chip. YTD436 supports layer 1 (physical layer) control function conforming to ITU-T Recommendation I.430 and fully supports layer 2 (LAPD protocol) function conforming to ITU-T Recommendations Q.920 and Q.921. ETSI (European Telecommunication Standards Institute) and North American standard operating modes are also supported. In addition, YTD436 includes layer 3 processor interface function which operate in DMA transfer mode or I/O transfer mode. This gives a great advantage for mounting and functional designing of both "active" (CPU on board) terminal equipment and "passive" (no CPU on board) PC cards. The layer 1 function has a built-in S/T reference point analog driver/receiver to support the S/T reference point interface. In order to support the U interface, YTD436 also has a I.430 TTL interface (no built-in analog driver/receiver) suitable for connecting to an NT1 chip or a DSU module.
YTD436 CATALOG CATALOG No.:4TD436A41 2005.1
Features
1. Layer 1 function
* Conforms to ITU-T Recommendation I.430 (1992 edition) and TTC Standard JT-I430 (1997 edition) (default) - 192 kbps transmission rate - Interface structure : 2B + D (B = 64 kbps, D = 16 kbps) - Frame assembling and disassembling function - Collision control (built-in random number (Ri) reset), priority control (built-in retransmission control), and state transition control - Programmable T3 and T4 timers * Supports ETSI ETS 300 012 (April 1992) and ANSI T1.605 operating modes * Leased line capability (JT-I430-a) * Built-in driver and receiver - I.430 TTL interface (when the driver / receiver is disconnected) - No external relay or common-mode choke needed - Supports 1-to-2 pulse transformer * Abundant Test functions (for testing and maintenance) - Demo mode in which no switch simulator is needed. - Three kinds of loop-back modes (Loop-back 1 to 3) - INFO signals output for testing - Test pulse output for pulse shape check * Multiframing capability * INFO1 transmission and INFO4 reception monitor pins * Power down monitor pin * I.430 transmission frame phase adjustment function
2. Layer 2 function
* Conforms to ITU-T Recommendation Q.920 (1992 edition) and Q.921 (1997 edition) and TTC Standard JT-Q920 (1993 edition) and JT-Q921 (1998 edition) - HDLC frame control (Flag control, FCS generation/checking, Automatic zero insertion/deletion, Abort pattern transmission/detection, etc.) - LAPD status control (Sequence control, Flow control, SAPI control) - Built-in timer for time-out check * Supports ETSI ETS 300 125 (September 1991), National ISDN-1/2, AT&T 5ESS 5E9 and Nortel DMS-100 S208-6 operating modes * Multilink capability (circuit switching x 2 links, packet switching/teleaction communications x 2 links) * Automatic assigned TEI/non-automatic assigned TEI (VC/PVC) * Leased line mode (disable layer 2 function)
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3. Layer 3 interface function
* Connects to 8-bit or 16-bit microprocessor (8086 family, 80186 family, 6800 family, 68000 family) * Operates in one of two data transfer modes : - DMA transfer mode (with the built-in 16-bit address DMA controller) - I/O transfer mode (with the built-in FIFO) * Primitive logical interface
4.
B channel interface
* Data rate setting : 64 k, 56 k and 32 kbps * Serial mode - B channel I/O clock selection function * Internal clock mode Inputs/outputs the B channel data with 64 k, 56 k or 32 kHz internal clock * External clock mode (PCM Highway mode) Inputs/outputs the B channel data with a 128 k to 2048 kHz external clock - B channel selection function * Internal clock mode Selects/switches B channel I/O pins * External clock mode (PCM Highway mode) Selects/switches B channel time slots * Parallel mode - LSB/MSB switching function - Bit shift function - Data transfer mode * DMA transfer mode with the DMA request function * I/O transfer mode with the built-in FIFO
5.
Low-power operation (Host processor clock control function, Powerdown mode)
6. 7. 8.
High-performance CMOS technology 100-pin SQFP DigitalSupply Voltage (+5V or +3.3V ), Analog +5V supply
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Applications
* ISDN telephone * Video telephone * Telemeter * PBX * Terminal adapter (TA) * Other ISDN terminals
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Functional Comparison of YAMAHA ISDN S/T Interface LSIs
FUNCTION Layer 1 ITU-T Recommendation I.430 TTC Standard JT-I430 Q.920 Q.921 JT-Q920 JT-Q921 YTD410 1992 edition 1993 edition 1992 edition 1993 edition YM7405B 1992 edition 1993 edition 1992 edition 1993 edition YTD418 1992 edition 1993 edition 1992 edition 1993 edition YTD423 1992 edition 1993 edition 1992 edition 1993 edition External [YTD421B] 2 2 External [YTD421B] 2 2 DMA Transfer or I/O Transfer Internal DMA Transfer or I/O Transfer 32, 56, 64 +5 +5 +5 YTD436 1992 edition 1997 edition 1992 edition 1997 edition 1993 edition 1998 edition
ITU-T Recommendation Layer 2 (LAPD) TTC Standard
ETSI ETS 300 012, ETS 300 125 North American Switches National ISDN-1/2, AT&T 5ESS, Nortel DMS-100 S/T Reference Point Analog Driver/Receiver Maximum D Channel Links
Circuit Switching Dch Packet Switching (Teleaction Communication) Internal 1 1
Internal 2 2
Internal 2 2 (2) DMA Transfer or I/O Transfer Internal DMA Transfer or I/O Transfer
D Channel Layer 3 Data Transfer Method HDLC Controller and DMA Controller for B Channel Data
DMA Transfer
DMA Transfer
DMA Transfer
External
External
External
B Channel Data Transfer Method
-
-
-
(Note 1)
32, 56, 64 +5 or +3.3
B Channel Internal Clock Mode (kHz) B Channel External Clock Mode
56, 64 +5
64
64
Clock Output Function for MPU
Signal Output Function for Testing
Supply Voltage (V) Power Consumption during Operation [typ.] (mW)
(Note 2)
65 2 125 30 75 21 80 Pin QFP 85 1 100 pin SQFP 75 (@+5V) 40 (@+3.3V) less than 0.5
Power Consumption during Sleep [typ.] (mW) Package
(Note 3)
100 pin SQFP
80 pin QFP 100 pin TQFP
80 pin QFP 100 pin TQFP
Note 1: Note 2: Note 3:
DMA Transfer: Request function only I/O transfer: 4 byte FIFO With respect to Digital Supply Voltage State at Line interface disconnection + Power down (SLEEP state)
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BLOCK DIAGRAM
User Network Interface Block Diagram
YTD436 is the most-suited LSI for terminal equipment such as ISDN telephones and video telephones and for PHS base stations. YTD436 contains layer 1 and layer 2 functions, analog driver/receiver for the S/T reference point, DMA request function for B channel data transfer, and DMA controller for D channel data transfer. Because of this, terminal equipment can be optimally configured by adding few circuits such as the layer 3 control processor.
S
TE1 (ISDN terminal) NT2 (PBX, etc...)
T
NT1 (DSU)
U
ISDN Network
R
TE2 Non-ISDN terminal
S
(
(
TA (Terminal Adapter)
S/T
TE1
R
TE2
S/T
TE1
U YTD436
DSU with built-in DSU
YTD428 (DSU)
User's premises
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YTD436 Peripheral LSI Interface Block Diagram
B1, B2 LI1 LI2
YTD436
LO1 LO2 A0 A15 D0 D15 R/W CS CS
Memory
A0 - D0 A15 D7 R/W CS
Peripheral LSI
A0 A15 D0 D15 R/W
Power supply detection circuit
Decoder
System address bus (A0 - A15)
System data bus (D0 - D15)
Control signal bus
A0 A15
D0 - R/W D15
Clock
MPU
(8086 , 68000 etc.)
System interrupt controller
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-8SYNC HW/B1, B2 bit
B channel control block Internal bus
B1 channel buffer
AMI/NRZ DPLL
CLKOUT
Transformer receiver B1 channel buffer B2 channel buffer Frame synchronization B2 channel buffer Bch interface
B
Clock generator
YTD436 Internal Block Diagram
To internal clock
HRD, LRD
Multi-frame control Frame disassembly
D D,E
HTD, LTD
HDLC frame disassembly
Internal controller
Bch FIFO
Priority, collision control
S B Q NRZ/AMI D
Buffer Buffer
MPU interface
Dch FIFO Dch DMAC
Microprocessor bus
Transformer driver
Layer 1 control block
Frame assembly
HDLC frame assembly
Buffer
Driver/Receiver block
Layer 2 control block
Layer 3 interface block
Pin Assignments
CX2 LICT LI1 HTD LTD HRD LRD PSDET INF4 INF1 PDOWN PDET PDSEL RESET DVDD DVSS X2 X1 CKOSEL CLKOUT RM CS R/W / WR MWR AS / RD
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
YTD436-S 100pin SQFP
MRD INT DMARQT1 DMARQT2 DMARQR1 DMARQR2 DMAAK1 DMAAK2 BGACK BG / HLDAK BR / HLDRQ DTACK / READY DVDD SYSCLK DVSS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
LI2 CX1 AVSS LO1 AVDD LO2 RX 80/68 16/8 TEST1 VDSEL CLKSEL WAKEUP RBHW / RB1 DVSS TBHW / RB2 RSYNC / TB1 TSYNC / TB2 EXTCLK / CL64K CL128K / CL32K CL56K CL8K CL4K AEN A15
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A14 A13 A12 A11 A10 A9 DVSS DVDD A8 A7 A6 A5 A4 A3 A2 A1 A0 / LBE UBE DVSS D15 D14 D13 D12 D11 D10
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Supply Voltage Input Voltage AVI Storage Temperature Ts t g - 0.3 - 50 AVDD + 0.3 + 125 V C Symbol VDD DV I Min. - 0.3 - 0.3 Max. + 7.0 DVDD + 0.3 Unit V V
(Based on DVSS = AVSS = 0.0 V)
Recommended Operating Conditions
Parameter Symbol DVDD Supply Voltage AVDD Operating Temperature Top VDSEL="L" 3.0 4.75 - 30 3.6 5.25 85 V V C Condition VDSEL="H" Min. 4.75 Max. 5.25 Unit V
(Based on DVSS= AVSS = 0.0 V)
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DC Characteristics
When DVDD = 5 V 5 %, AVDD = 5 V 5 % (VDSEL="H", Top = - 30 to + 85 C)
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage High-Level Output Voltage Low-Level Output Voltage Low-Level Output Voltage Leakage Current Off-State Leakage Current Power Supply Current (Digital block) (CMOS) (CMOS) (TTL) (TTL) (CMOS) (CMOS) (TTL) (TTL) (Open-D) Symbol VDIH VDIL VDIH VDIL VDOH VDOL VDOH VDOL VDOL IL ILZ DIDD (Note 7, 9) (Note 6, 10) Power Supply Current (Analog block) AIDD (Note 7, 10) (Note 8, 10) 0.1 4.8 0.4 0.1 mA mA mA mA (Note 5) (Note 6) Condition (Note 1) (Note 1) (Note 2) (Note 2) |IDOH| < 10 A |IDOL| < 10 A (Note 3) (Note 3) (Note 4) -10 -10 10.2 2.7 0.4 0.4 10 10 D V DD - 0 . 4 DVSS + 0.4 2.2 0.8 Min. 0.8DVDD 0.2DVDD Typ. Max. Units V V V V V V V V V A A mA
------------------ ---------------
---------------
Note 1: With respect to X1, PSDET, PDET, PDSEL, WAKEUP, RESET, CLKSEL, TEST1, VDSEL pins (except for the analog pins). Note 2: With respect to other pins (except for the analog pins). Note 3: CLKOUT pin other output pins
--------- ------------
Test condition: IDOH = - 1.0 mA, IDOL = 2.0 mA Test condition: IDOH = - 0.4 mA, IDOL = 1.2 mA
Note 4: HTD, LTD, INT pin Test condition : IDOL = 1.2 mA INF1 pin RBHW pin Test condition : IDOL = 3 mA Test condition : RL = 500
------------
Note 5: With respect to cases in which D0 - D15, and A0 - A15 pins are in the input state and MWR and ---------- MRD pins are in Hi-Z state. Note 6: RUN state (connecting with a B channel, transferring all "0", SYSCLK = 8 MHz, using internal driver/receiver, assuming as VDIH = DVDD, VDIL = DVSS ) Note 7: SLEEP state Note 8: SLEEP state + Line interface disconnection Note 9: When SYSCLK is stopped. Note 10: When using internal driver/receiver
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When DVDD = 3.3 V 0.3 V, AVDD = 5 V 5 % (VDSEL="L", Top = - 30 to + 85 C)
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Low-Level Output Voltage Leakage Current Off-State Leakage Current Power Supply Current (Digital block) (Open-D) Symbol VDIH VDIL VDOH VDOL VDOL IL ILZ DIDD (Note 4, 6) (Note 3, 7) Power Supply Current (Analog block) AIDD (Note 4, 7) (Note 5, 7) 0.1 4.8 0.4 0.1 mA mA mA mA (Note 2) (Note 3) |IDOH| < 0.4 mA |IDOL| < 1.2 mA (Note 1) -10 -10 4.9 D V DD - 0 . 4 DVSS + 0.4 0.4 10 10 Condition Min. 0.8DVDD 0.2DVDD Typ. Max. Units V V V V V A A mA
--------- ------------
Note 1: HTD, LTD, INT, INF1 pin Test condition : IDOL = 1.2 mA RBHW pin Test condition : RL = 500
------------
Note 2: With respect to cases in which D0 - D15, and A0 - A15 pins are in the input state and MWR and ---------- MRD pins are in Hi-Z state. Note 3: RUN state (connecting with a B channel, transferring all "0", SYSCLK = 8 MHz, using internal driver/receiver, assuming as VDIH = DVDD, VDIL = DVSS ) Note 4: SLEEP state Note 5: SLEEP state + Line interface disconnection Note 6: When SYSCLK is stopped. Note 7: When using internal driver/receiver
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PACKAGE OUTLINE
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